The AES IP accepts 8/16/32 bits input data (merged to a 128-bit data in the IP) and generates a corresponding 128-bit cipher/plain text output word using a supplied 128, 192 or 256-bit AES key. It supports encryption/decryption function and provides the interface that can be connected with processor or user logic in HME FPGA.

Features

• Configurable cores provided for encryption or decryption

• AES key

• Supports 128, 192 or 256-bit key size

• Supports dynamic configurable key

• Simple external interface

• Supports 8, 16 and 32 bits interface for M5&M7
  

• Supports 32-bit interface for HME-HR3

• Supports ECB and CBC mode

• Supports ECB and CBC mode for M5&M7
  

• Supports ECB mode for HME-HR3