Features

• Supports data width up to 128-bit with depth up to 1K-bit

• Supports different input and output data widths
  

• FIFO Supports both synchronous and asynchronous FIFO
  

• Supports wfull/rempty status flag
  

• Optional synchronous clear inputs for both read and write
  

• Optional almost_full/almost_empty status flag to indicate only one more data can be written/read before FIFO is full/empty
  

• Optional prog_full/prog_empty status flag

• Supports 4 types of programmable full flag generation:

1. Single threshold constant

2. Single threshold with dedicated input port

3. Assert and negate threshold constants

4. Assert and negate thresholds with dedicated input ports
   

• Optional count vector(s) (wr_data_cnt and rd_data_cnt) provide visibility into number of data words currently in the FIFO, synchronized to either clock domain

• Four optional handshake signals (wr_ack, rd_ack, overflow, underflow) provide feedback (acknowledgment or rejection) in response to write and read requests in the prior clock cycle
  

• Invalid read or write requests are rejected without affecting the FIFO state. When FIFO is full, data can't write to FIFO anymore, the write data will be omitted. When FIFO is empty, data can't read out anymore

• Up to 200MHz performance

• Supports First Word Fall Through function

• Supports AHB interface protocols (AHB interface FIFO)

• The interface type of write port and read port can be configured (AHB interface FIFO, users can choose AHB interface or not)

• Base Address can be configured (AHB interface FIFO)